Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) Review

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(More customer reviews)This is a must-have book for test engineers or test software developers in the integrated ckts industry. The book discusses how to optimize test time, tester memory and test hardware. Treatment of complex economics issues is thoughtfully presented. The methods are not patented and can be useful to the average test engineer.

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Test Resource Partitioning for System-on-a-Chip is abouttest resource partitioning and optimization techniques forplug-and-play system-on-a-chip (SOC) test automation. Plug-and-playrefers to the paradigm in which core-to-core interfaces as well ascore-to-SOC logic interfaces are standardized, such that cores can beeasily plugged into "virtual sockets" on the SOC design, and coretests can be plugged into the SOC during test without substantialeffort on the part of the system integrator. The goal of the book isto position test resource partitioning in the context of SOC testautomation, as well as to generate interest and motivate research onthis important topic.SOC integrated circuits composed of embedded cores are nowcommonplace. Nevertheless, There remain several roadblocks to rapidand efficient system integration. Test development is seen as a majorbottleneck in SOC design, and test challenges are a major contributorto the widening gap between design capability and manufacturingcapacity. Testing SOCs is especially challenging in the absence ofstandardized test structures, test automation tools, and testprotocols.Test Resource Partitioning for System-on-a-Chip responds to apressing need for a structured methodology for SOC test automation. Itpresents new techniques for the partitioning and optimization of thethree major SOC test resources: test hardware, testing time and testdata volume.Test Resource Partitioning for System-on-a-Chip paves the wayfor a powerful integrated framework to automate the test flow for alarge number of cores in an SOC in a plug-and-play fashion. Theframework presented allows the system integrator to reduce test costand meet short time-to-market requirements.

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